dc.contributor.author | Aretxabaleta Astoreka, Iker | |
dc.contributor.author | Martínez de Alegría Mancisidor, Iñigo | |
dc.contributor.author | Gárate Añibarro, José Ignacio | |
dc.contributor.author | Ugalde Olea, Unai | |
dc.contributor.author | Martín González, José Luis | |
dc.date.accessioned | 2023-01-17T14:34:01Z | |
dc.date.available | 2023-01-17T14:34:01Z | |
dc.date.issued | 2022-03 | |
dc.identifier.citation | IET Power Electronics 15(4) : 317-324 (2022) | es_ES |
dc.identifier.issn | 1755-4543 | |
dc.identifier.uri | http://hdl.handle.net/10810/59318 | |
dc.description.abstract | The shorter switching times of silicon carbide (SiC) MOSFETs enable power converters to operate at higher frequencies than with silicon IGBTs. However, because SiC MOSFET die sizes are still relatively small, several devices have to be connected in parallel to cope with the high current ratings demanded. For the total current to be evenly distributed among all the MOSFETs, the gate circuit and power layout must meet stringent symmetry requirements. However, space limitations on the circuit surface hinders the achievement of full symmetries on both the power and gate layouts because they constrain one another. This paper proposes a solution for safely paralleling discrete SiC MOSFETs while decoupling the gate and power layout designs. It requires placing one BJT-based fast current amplifier as close as possible to each MOSFET rather than using just one to feed all the MOS gates. This reduces the noise in the received gating signals and, more importantly, reduces the sensitivity of driver-gate path geometric / electric mismatches. This makes it possible to safely relax the symmetry requirements for the gating circuitry, thereby providing designers with more freedom to achieve better symmetry in the power layout. | es_ES |
dc.description.sponsorship | This work was supported in part by the Government of the Basque Country within the fund for research groups of the Basque University system IT978-16 and by the ELKARTEK research program (project ENSOL2-KK-2020/00077) and by the MCIN/AEI/10.13039/501100011033 within the project PID2020-115126RB-I00. | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Wiley | es_ES |
dc.relation | info:eu-repo/grantAgreement/MCIN/PID2020-115126RB-I00 | es_ES |
dc.rights | info:eu-repo/semantics/openAccess | es_ES |
dc.title | Multiple current amplifier-based gate driving for parallel operation of discrete SiC MOSFETs | es_ES |
dc.type | info:eu-repo/semantics/article | es_ES |
dc.rights.holder | This is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivsLicense, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made. © 2022 The Authors. IET Power Electronics published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology | es_ES |
dc.relation.publisherversion | https://ietresearch.onlinelibrary.wiley.com/doi/full/10.1049/pel2.12232 | es_ES |
dc.identifier.doi | 10.1049/pel2.12232 | |
dc.departamentoes | Tecnología electrónica | es_ES |
dc.departamentoeu | Teknologia elektronikoa | es_ES |