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dc.contributor.authorDe Marcos Arocena, Ander ORCID
dc.contributor.authorRobles Pérez, Endika ORCID
dc.contributor.authorUgalde Olea, Unai ORCID
dc.contributor.authorMartínez de Alegría Mancisidor, Iñigo ORCID
dc.contributor.authorAndreu Larrañaga, Jon ORCID
dc.date.accessioned2023-02-15T14:23:16Z
dc.date.available2023-02-15T14:23:16Z
dc.date.issued2023-02-10
dc.identifier.citationMachines 11(2) : (2023) // Article ID 267es_ES
dc.identifier.issn2075-1702
dc.identifier.urihttp://hdl.handle.net/10810/59853
dc.description.abstractThe DC-Link capacitor plays a crucial role as far as power density and reliability are concerned: it occupies approximately 40% of the inverter, and causes approximately 30% of its failures. Asymmetrical dual three-phase (ADTP) multiphase arrangements are gaining relevance in the automotive sector for powertrain applications. This work focuses on reducing the impact that the widely used double zero sequence injection (DZSI) family of PWM techniques have on such a bulky and failure-prone component in an ADTP arrangement by means of interleaving techniques. By using the double Fourier integral formalism, the input current spectra and the overall performance of these PWM techniques have been derived, in terms of current rms value and voltage ripple in the DC-Link capacitor. Simulations have shown that choosing an adequate interleaving scheme and angle considerably relieves both current and voltage stresses on the DC-Link capacitor compared to noninterleaved operation. Reductions of 84% current rms and 86% voltage ripple have been achieved at static operating points. Finally, by averaging the rms current over WLTP standard driving cycle, reductions up to 26% have been obtained under more realistic conditions. All this would enhance the reliability and reduce the size of the onboard capacitors in future electric vehicles.es_ES
dc.description.sponsorshipThis work was supported in part by the Government of the Basque Country within the fund for research groups of the Basque University system IT1440-22 and by the MCIN/AEI/10.13039/501100011033 within the project PID2020-115126RB-I00, as well as the support of the UPV/EHU pre-doctoral programme (PIF20-305).es_ES
dc.language.isoenges_ES
dc.publisherMDPIes_ES
dc.relationinfo:eu-repo/grantAgreement/MCIN/PID2020-115126RB-I00es_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/es/*
dc.subjectmultiphasees_ES
dc.subjectinterleavinges_ES
dc.subjectasymmetrical dual three-phasees_ES
dc.subjectdouble zero-sequence injection (DZSI) PWMes_ES
dc.subjectDC-Link capacitores_ES
dc.subjectDC-Link current spectrumes_ES
dc.titleInterleaving Modulation Schemes in Asymmetrical Dual Three-Phase Machines for the DC-Link Stress Reductiones_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.rights.holder© 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).es_ES
dc.relation.publisherversionhttps://www.mdpi.com/2075-1702/11/2/267es_ES
dc.identifier.doi10.3390/machines11020267
dc.departamentoesTecnología electrónicaes_ES
dc.departamentoeuTeknologia elektronikoaes_ES


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© 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Except where otherwise noted, this item's license is described as © 2023 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).