AXI Lite redundant on-chip bus interconnect for high reliability systems
Ver/
Fecha
2023-04-27Autor
Lázaro Arrotegui, Jesús
Astarloa Cuéllar, Armando Fermín
Zuloaga Izaguirre, Aitzol
Jiménez Verde, Jaime
Metadatos
Mostrar el registro completo del ítem
IEEE Transactions on Reliability : (2023)
Resumen
Nowadays, system-on-chips have become critical since they support more and more safe applications due to their flexibility. However, they are susceptible to single-event upsets because the memory cell size has significantly shrunk. This article presents a triple redundant on-chip interconnect bus that provides low-speed peripherals with high reliability. In addition to correcting single errors and detecting duplicated ones, the proposed circuit offers zero latency and is transparent for both the embedded processor and the peripherals. These characteristics make it suitable for hard real-time applications. At the same time, the impact on area and power consumption is minimal.