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dc.contributor.authorUrbina, Marcelo
dc.contributor.authorMoreira Ciruelos, Naiara
dc.contributor.authorRodríguez, Mikel
dc.contributor.authorAcosta, Tatiana
dc.contributor.authorLázaro Arrotegui, Jesús
dc.contributor.authorAstarloa Cuéllar, Armando Fermín
dc.date.accessioned2019-03-12T13:51:53Z
dc.date.available2019-03-12T13:51:53Z
dc.date.issued2018-03
dc.identifier.citationEnergies 11(3) : (2018) // Article ID 510es_ES
dc.identifier.issn1996-1073
dc.identifier.urihttp://hdl.handle.net/10810/31987
dc.description.abstractNowadays, the incorporation and constant evolution of communication networks in the electricity sector have given rise to the so-called Smart Grid, which is why it is necessary to have devices that are capable of managing new communication protocols, guaranteeing the strict requirements of processing required by the electricity sector. In this context, intelligent electronic devices (IEDs) with network architectures are currently available to meet the communication, real-time processing and interoperability requirements of the Smart Grid. The new generation IEDs include an Field Programmable Gate Array (FPGA), to support specialized networking switching architectures for the electric sector, as the IEEE 1588-aware High-availability Seamless Redundancy/Parallel Redundancy Protocol (HSR/PRP). Another advantage to using an FPGA is the ability to update or reconfigure the design to support new requirements that are being raised to the standards (IEC 61850). The update of the architecture implemented in the FPGA can be done remotely, but it is necessary to establish a cyber security mechanism since the communication link generates vulnerability in the case the attacker gains physical access to the network. The research presented in this paper proposes a secure protocol and Intellectual Property (IP) core for configuring and monitoring the networking IPs implemented in a Field Programmable Gate Array (FPGA). The FPGA based implementation proposed overcomes this issue using a light Layer-2 protocol fully implemented on hardware and protected by strong cryptographic algorithms (AES-GCM), defined in the IEC 61850-90-5 standard. The proposed secure protocol and IP core are applicable in any field where remote configuration over Ethernet is required for IP cores in FPGAs. In this paper, the proposal is validated in communications hardware for Smart Grids.es_ES
dc.description.sponsorshipThis work has been supported by the Ministerio de Economia y Competitividad of Spain within the project TEC-2017-84011-R and it has been carried out inside the Research and Education Unit UFI11/16 of the UPV/EHU and partially supported by the Basque Government within the fund for research groups of the Basque university system IT978-16 and within the project TFactory ER-2014/0016. Also, FEDER funds, UPV/EHU, and Universidad de las Fuerzas Armadas ESPE through a PhD scholarship funding are acknowledged.es_ES
dc.language.isoenges_ES
dc.publisherMDPIes_ES
dc.relationinfo:eu-repo/grantAgreement/MINECO/TEC-2017-84011-Res_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/es/*
dc.subjectcyber-securityes_ES
dc.subjectConfiguration Over Ethernet secure (COEsec)es_ES
dc.subjectField Programmable Gate Array (FPGA)es_ES
dc.subjectHigh-availability Seamless Redundancy (HSR)es_ES
dc.subjectIEC 61850es_ES
dc.subjectindustrial communicationes_ES
dc.subjectSubstation Automation Systems (SAS)es_ES
dc.subjectcryptographyes_ES
dc.subjectSmat Grides_ES
dc.titleSecure Protocol and IP Core for Configuration of Networking Hardware IPs in the Smart Grides_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.rights.holderThis is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).es_ES
dc.rights.holderAtribución 3.0 España*
dc.relation.publisherversionhttps://www.mdpi.com/1996-1073/11/3/510es_ES
dc.identifier.doi10.3390/en11030510
dc.departamentoesTecnología electrónicaes_ES
dc.departamentoeuTeknologia elektronikoaes_ES


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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
Except where otherwise noted, this item's license is described as This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).