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dc.contributor.authorVillalta Bustillo, Igor
dc.contributor.authorBidarte Peraita, Unai ORCID
dc.contributor.authorSantos, Gorka
dc.contributor.authorMatallana Fernandez, Asier ORCID
dc.contributor.authorJiménez Verde, Jaime
dc.date.accessioned2024-06-03T13:52:16Z
dc.date.available2024-06-03T13:52:16Z
dc.date.issued2014-11-26
dc.identifier.citationDesign of Circuits and Integrated Systems, Madrid, Spain, 2014 : 1-6 (2014)es_ES
dc.identifier.isbn978-1-4799-5743-9
dc.identifier.urihttp://hdl.handle.net/10810/68319
dc.descriptionArticulo Congreso DCIS 2014es_ES
dc.description.abstractThis paper presents a fault injection method for SEU (Single Event Upset) emulation in FPGAs based on loading at the programmable logic a configuration file with an erroneous bit. A "Xilinx Zynq®-7000 All Programmable SoC" device has been used to implement it, which combines a hard microprocessor (Processing System PS) with Programmable Logic (PL). The emulation tool is fully implemented on the Zynq chip, which means that neither additional external equipment nor PCB modifications are needed. Communications to external devices that slow down the configuration process are avoided, so a high fault-injection rate is achieved. Previous works consider including fault injection circuitry at the PL. This circuitry can be affected by a faulty configuration file, leading the device to an unrecoverable state, which is named as "injection side effects". In the method proposed in this paper the injection is implemented in the processing system of the Zynq device, making the injection system independent to the programmable logic and avoiding the previously mentioned effect. This method allows using complete bitstreams, partial bitstreams and one-frame bitstreams to inject faults. A comparison is done so as to find the most appropriate bitstream type.es_ES
dc.description.sponsorshipThis work was carried out in the R&D Unit UFI11/16 of the UPV/EHU, and supported by the Ministerio de Ciencia e Innovacion of Spain within the projects TEC2011–28250-C02-01/2, by the UPV/EHU within the project US13/13 and by the Basque Governments Department of Education, Universities and Research within the research fund of the Basque university system IT394–10.es_ES
dc.language.isoenges_ES
dc.publisherIEEEes_ES
dc.relationinfo:eu-repo/grantAgreement/MCIN/TEC2011–28250-C02-01/2es_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.subjectSEUes_ES
dc.subjectFPGAes_ES
dc.subjectemulationes_ES
dc.subjectfault injectiones_ES
dc.subjectfault tolerancees_ES
dc.subjectZYNQes_ES
dc.titleFault Injection System for SEU Emulation in Zynq SoCses_ES
dc.typeinfo:eu-repo/semantics/conferenceObjectes_ES
dc.rights.holder© 2014 IEEEes_ES
dc.relation.publisherversionhttps://ieeexplore-ieee-org.ehu.idm.oclc.org/document/7035579es_ES
dc.identifier.doi10.1109/DCIS.2014.7035579
dc.departamentoesTecnología electrónicaes_ES
dc.departamentoeuTeknologia elektronikoaes_ES


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