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dc.contributor.authorMatallana Fernandez, Asier ORCID
dc.contributor.authorAndreu Larrañaga, Jon ORCID
dc.contributor.authorGárate Añibarro, José Ignacio
dc.contributor.authorAretxabaleta Astoreka, Iker
dc.contributor.authorKortabarria Iparragirre, Iñigo ORCID
dc.date.accessioned2024-06-18T14:06:53Z
dc.date.available2024-06-18T14:06:53Z
dc.date.issued2018-06-05
dc.identifier.citationPCIM Europe 2018; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany : 1-8 (2018)es_ES
dc.identifier.isbn978-3-8007-4646-0
dc.identifier.urihttp://hdl.handle.net/10810/68496
dc.descriptionArticulo Congreso PCIM 2018 - VDEes_ES
dc.description.abstractThe aim of this work is to design a DC bus for a silicon carbide power converter whose application is the automotive sector. This power converter works at high voltage and current levels with high frequencies signals, so a DC bus design with low impedance is necessary. Moreover, current has to flow homogeneously to avoid imbalances between bus capacitors. In order to get this goal, different design criteria are explained. These criteria are based on the theory of semiconductor parallelization, where the control and equal distribution of parasitic impedances is fundamental to get a modular bus structure, where the symmetrical design and mutual coupling effect of different layers produce a current balance over the wide and long copper areas of this DC bus.es_ES
dc.description.sponsorshipThis work has been supported by the Department of Education, Linguistic Policy and Culture of the Basque Government within the fund for research groups of the Basque university system IT978-16 and the research program ELKARTEK as the project KT4TRANS (KK-2015/00047 and KK-2016/00061). The support of the Ministerio de Economía y Competitividad of Spain within the project DPI2014-53685-C2-2-R and FEDER funds. As well as, the program to support the education of researches of the Basque Country PRE_2017_2_0008 and technical and human support provided by IZO-SGI SGIker of UPV/EHU and European funding (ERDF and ESF).es_ES
dc.language.isoenges_ES
dc.publisherVDEes_ES
dc.relationinfo:eu-repo/grantAgreement/MINECO/DPI2014-53685-C2-2-Res_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.titleAnalysis and Design of a Multilayer DC Bus With Low Stray Impedance and Homogenous Current Distributiones_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.rights.holder© 2018 VDE VERLAGes_ES
dc.relation.publisherversionhttps://ieeexplore-ieee-org.ehu.idm.oclc.org/document/8403058es_ES
dc.departamentoesTecnología electrónicaes_ES
dc.departamentoeuTeknologia elektronikoaes_ES


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