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      Functional Verification for SEU Emulation in FPGA Designs 

      Villalta Bustillo, Igor; Bidarte Peraita, Unai ORCID; Kretzchmar, Uli; Santos, Gorka; Matallana Fernandez, Asier ORCID (2014-09-17)
      In this paper techniques to detect failures in a FPGA are presented and their application to SEU (Single Event Upset) emulation applications is discussed. SEU emulation in FPGAs consists on programming the device with a ...