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Functional Verification for SEU Emulation in FPGA Designs
; Bidarte Peraita, Unai
; ; ; Matallana Fernandez, Asier (2014-09-17)
In this paper techniques to detect failures in a FPGA are presented and their application to SEU (Single Event Upset) emulation applications is discussed. SEU emulation in FPGAs consists on programming the device with a ... -
Treinta años de Arqueología Medieval en España
(Archaopress, 2018-08)This book presents, in sixteen papers, recent developments and some of the main topics seen in academic Medieval Archaeology studies in Spain. The papers explore some of the emergent and consolidated topics of the discipline, ... -
Analysis of impedance and current distributions in parallel IGBT design
Matallana Fernandez, Asier; Andreu Larrañaga, Jon ; ; Martínez de Alegría Mancisidor, Iñigo ; Kortabarria Iparragirre, Iñigo (IEEE, 2017-08-07)
Power electronic applications need high voltage and current ranges which are impossible to obtain with discrete devices. Parallelization technique is a solution to increase power converter current capacity. Current ... -
Analysis and modelling of IGBTs parallelization fundamentals
Matallana Fernandez, Asier; Andreu Larrañaga, Jon ; ; ; Planas Fullaondo, Estefanía (IEEE, 2016-12-22)
In some power electronic applications, with high current and voltage ranges, discrete devices are not enough unless parallelization techniques are employed. IGBTs are one of the most common and widespread power electronic ...